![]() It is expensive and difficult to implement in the current 2 dimensional design, however, it is technically doable, and the first company which does it successfully, will have computers 100's of times faster and still running cool, something which would produce major innovations in many fields and are only accessbile currently through expensive and difficult to program ASIC/FPGA configurations. L1 cache can be accessed at GHz frequencies, the same as processor operations, unlike RAM access 400x slower. The pathetically tiny L1 cache sizes may be the sweetspot for the price, but not the performance. With the inclusive cache design found on Intel CPUs, not only does a larger L1 cache increase latency, but it reduces the usable size of the L2 cache, which is an additional reason to not have a larger L1 cache, especially in the budget CPU market.Īctually L1 cache size IS the biggest bottleneck for speed in modern computers. The exclusive cache design meant that a larger L1 cache could be used in conjunction with a small L2 cache without wasting the little available space in the L2 cache as would happen with an inclusive cache. AMD sold a lot of budget CPUs with L2 cache sizes as small as 128KB, so having 128KB of L1 cache with exclusive cache design meant that the actual cache size of a 128KB L1 and 128KB L2 cache CPU was 256KB total. These CPUs featured an exclusive cache design, which means that a second copy of data in the L1 cache is NOT kept in the L2 cache, which saves room to store other data in the L2 cache. The AMD Athlon and Athlon 64 CPUs came with a large 128KB of L1 cache (64KB data and 64KB instruction). Then a new smaller and lower latency level 2 cache ranging from 256KB to 1MB in size is added to the CPU. The large high latency L2 caches found on the Pentium M (with 2MB L2 cache) and Core2Duo (with 6MB L2 cache) CPUs is turned in to a level 3 cache. This is done by keeping the low latency 32K L1 data and instruction caches the same size. But there is a solution to this problem that will let applications that work optimally with a small low latency cache and a larger higher latency cache to both run quickly. Making the level 1 cache bigger may improve over all performance a bit by allowing applications that would make use of a bigger cache run faster, but it would also cause applications that only make use of a smaller L1 cache run a bit slower due to higher latency. These two requirements have pulled against each other, resulting in the optimal size of the level 1 cache being about the same. But as CPUs have become faster, lower L1 cache latency is needed. If you have arrived to this post,ĭon't take all our answers here too seriously.Īs the transistor density of integrated circuits has become higher and higher, it has become possible to make larger caches without increasing the latency, and caches of the same size can be made with much lower latency. Because it's built in to the chip with a zero wait-state (delay) interface to the processor's execution unit, it is limited in size.ĮDIT: Please note that this answer is from 2009 and CPUs have evolvedĮnormously in the last 10 years. That program almost freezed the computer because for each random read a whole page was moved from RAM to cache and since that was done very often that simple program was draining out all bandwith leaving really few resources for the OS. I tried once creating a simple program that was accessing random locations in an array (of several MegaBytes): Also note that now there's a greater "culture" about cache and many programmers write "cache-friendly" code and/or use prefetech instructions to reduce latency. If L1 cache size didn't changed after 64kb it's because it was no longer worth. For L1 caches there should be some other charts (that vendors don't show) that make convenient 64 Kb as size.At wikipedia you can find a chart showing for example how unworth is making caches bigger than 1MB (actually bigger caches exist but you must keep in count that those are multiprocessor cores.).Doubling cache size does not double performance (even if physics allowed that size to work) for small sizes doubling gives much more than double performance, for big sizes doubling cache size gives almost no extra performance. ![]() Speed of electric signals (should be if not the speed of light, something of same order of magnitude):Įconomic cost (circuits at different cache levels may be different and certain cache sizes may be unworth) Cache size is influenced by many factors:
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